This invention generally relates to frequency divider circuits and, more particularly, to a frequency divider circuit selectively operable for providing a frequency divided representation of an input signal or, alternatively, an undivided representation of the input signal.
In various applications it is desirable to provide a frequency divider circuit whose operation can be selectively controlled for providing an output signal characterized by different frequencies. For example, in an electronic organ or the like, a rhythm unit may be operated in response to input clock signals for producing sound characteristics simulating a particular rhythm. The frequency composition of the rhythm may therefore be conveniently modified by suitably changing the pulse repetition rate or frequency of the input clock signal according to a preselected sequence. In a known application of the foregoing type it is particularly useful to provide means for selectively producing an output signal having a particular frequency or a frequency equal to one-half thereof.
A known circuit operable for providing an output signal alternatively characterized by a frequency f or f/2 consists of a source of input clock pulses coupled by a divide by two circuit to one input of a first AND gate of an AND-OR select circuit. The clock pulses are also directly coupled to a first input of a second AND gate of the AND-OR select circuit, both AND gates having outputs supplying an OR gate. A control signal is coupled directly to a second input of the second AND gate and through an inverter to a second input of the first AND gate. Thus, when the control signal is logically low, the first AND gate is enabled and an output is developed by the OR gate at a frequency equal to the frequency f of the clock pulses. On the other hand, when the control signal is logically high, the second AND gate is enabled and a signal is developed at the output of the OR gate having a frequency of f/2. Thus, by suitably establishing a logically low or logically high control signal an output signal is developed having a frequency of either f or f/2, where f is the frequency of the input clock signal.
In a system of the foregoing type, the control signal is typically asynchronously related to the input clock signal. As a result, depending upon the phase relationship between the input clock signal and the control signal, unwanted signal components, generally narrow spikes, are intermingled with the otherwise desired components of the output signal. These unwanted signal spikes frequently prove troublesome to the apparatus controlled by the output signal rendering its operation erratic.
A known method of eliminating these signal spikes is to provide ancillary circuitry for synchronizing the control signal with the input clock pulses. Needless to say, this technique involves added complexity in circuit design along with additional cost to implement a suitable system.